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general description the ds3988 is an 8-channel controller for cold-cathodefluorescent lamps (ccfls) used to backlight liquid crystal displays (lcds) in tv and pc monitor applica- tions. the ds3988 supports configurations of 1 to 8 lamps, and multiple ds3988 controllers can be cascad- ed to support applications requiring more than 8 lamps. applications lcd televisionslcd pc monitors features ? high-density ccfl controller for lcd tv and pcmonitor backlights ? can be easily cascaded to support more than 8 lamps ? minimal external components ? analog brightness control ? per-channel lamp control ensures equalbrightness among lamps and maximizes lamp life ? gate driver phasing minimizes dc supply currentsurges ? per-channel lamp fault monitoring for lampopen, lamp overcurrent, failure to strike, and overvoltage conditions ? accurate (?%) independent on-board oscillatorsfor lamp frequency (40khz to 80khz) and dpwm burst dimming frequency (22.5hz to 440hz) ? can be synchronized to external sources for thelamp and dpwm frequencies ? <10% to 100% dimming range ? programmable soft-start minimizes audibletransformer noise ? i 2 c-compatible serial port and on-board nonvolatile (nv) memory allow devicecustomization ? 8-byte nv user memory for storage of serialnumbers and date codes ? 4.5v to 5.5v single-supply operation ? -40? to +85? temperature range ? 48-lead tqfp (7mm x 7mm) package ds3988 8-channel cold-cathode fluorescent lamp controller ______________________________________________ maxim integrated products 1 ovd8 lcm8ga8 ovd7 ga7 ovd6lcm6 ga6 gb6 lcm7gb7 gb8 lcm1 ovd1 ga2 gb2 lcm2 ovd2 ga3 ovd3 gb3 lcm3 gb1 ga1 12 3 4 5 6 7 8 9 1011 12 3635 34 33 32 31 30 29 28 27 26 25 ovd4 gnd ga5 lcm5 gnd v cc ovd5 lcm4 gb4 ga4 gnd svm bright gndposc psync a0 losc lsync faultsda scl v cc 48-lead tqfp 7 x 7 x 1.0mm gb5 top view 4847 46 45 44 43 42 41 40 39 38 37 1314 15 16 17 18 19 20 21 22 23 24 ds3988 pin configuration rev 0; 4/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information typical operating circuit appears at end of data sheet. part temp range pin-package DS3988T -40? to +85? 48 tqfp DS3988T+ -40? to +85? 48 tqfp + denotes lead-free package. downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller 2 _____________________________________________________________________ absolute maximum ratings recommended operating conditions(t a = -40? to +85?.) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage on v cc , sda, and scl relative to ground.............................................-0.5v to +6.0v voltage on leads other than v cc , sda, and scl..-0.5v to (v cc + 0.5v), not to exceed +6.0v operating temperature range ...........................-40? to +85? eeprom programming temperature range .........0? to +70? storage temperature range .............................-55? to +125? soldering temperature...................see j-std-020 specification parameter symbol conditions min typ max units supply voltage v cc (note 1) 4.5 5.5 v input logic 1 v ih 0.7 x v cc v cc + 0.3 v input logic 0 v il -0.3 0.3 x v cc v svm voltage range v svm -0.3 v cc + 0.3 v bright voltage range v bright -0.3 v cc + 0.3 v lcm voltage range v lcm (note 2) -0.3 v cc + 0.3 v ovd voltage range v ovd (note 2) -0.3 v cc + 0.3 v gate-driver output chargeloading q g 20 nc electrical characteristics(v cc = +4.5v to +5.5v, t a = -40? to +85?.) parameter symbol conditions min typ max units supply current i cc g a , g b loaded with 600pf, 8 channels active 15 20 ma input leakage (digital pins) i l -1.0 +1.0 ? output leakage (sda, fault )i lo high impedance -1.0 +1.0 ? v ol1 i ol1 = 3ma 0.4 low-level output voltage(sda, fault) v ol2 i ol2 = 6ma 0.6 v low-level output voltage(psync, lsync) v ol3 i ol3 = 4ma 0.4 v low-level output voltage(ga, gb) v ol4 i ol4 = 4ma 0.4 v high-level output voltage(psync, lsync) v oh1 i oh1 = -1ma v cc - 0.4 v downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller _____________________________________________________________________ 3 electrical characteristics (continued)(v cc = +4.5v to +5.5v, t a = -40? to +85?.) parameter symbol conditions min typ max units high-level output voltage(ga, gb) v oh2 i oh2 = -1ma v cc - 0.4 v uvlo threshold? cc rising v uvlor 4.3 v uvlo threshold? cc falling v uvlof 3.7 v uvlo hysteresis v uvloh 100 mv svm threshold v svmt 1.8 2.0 2.2 v svm hysteresis v svmh 50 mv lcm and ovd source current 4 a lcm and ovd sink current 4 a lcm and ovd dc bias voltage v dcb 1.35 v lcm and ovd input resistance r dcb 50 k ? lamp off threshold v lot (note 3) 0.3 0.4 0.5 v lamp overcurrent threshold v loc (note 3) 1.8 2.0 2.2 v lamp regulation threshold v lrt (note 3) 0.9 1.0 1.1 v ovd threshold v ovdt (note 3) 0.9 1.0 1.1 v lamp frequency range f lf:osc 40 80 khz lamp frequency sourcefrequency tolerance f lfs:tol losc resistor ?% over temperature -5 +5 % lamp frequency receiverduty cycle f lfr:duty 40 60 % dpwm frequency range f d:osc 22.5 440.0 hz dpwm source frequencytolerance f dsr:tol posc resistor ?% over temperature -5 +5 % dpwm receiver duty cycle f dfe:duty 40 60 % dpwm receiverfrequency range f dr:osc 22.5 440.0 hz dpwm receiverminimum pulse width t dr:min (note 4) 25 ? bright voltage?inimumbrightness v bmin 0.5 v bright voltage?aximumbrightness v bmax 2.0 v gate-driver output rise/fall time t r /t f c l = 600pf 100 ns gan and gbn duty cycle (note 5) 44 % downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller 4 _____________________________________________________________________ i 2 c ac electrical characteristics (see figure 9) (v cc = +4.5v to +5.5v, timing referenced to v il(max) and v ih(min) , t a = -40? to +85?.) note 1: all voltages are referenced to ground, unless otherwise noted. currents into the ic are positive, out of the ic negative. note 2: during fault conditions, the ac-coupled feedback values are allowed to be outside the absolute max rating of the lcm orovd pin for up to 1 second. note 3: voltage with respect to v dcb . note 4: this is the minimum pulse width guaranteed to generate an output burst, which will generate the ds3988? minimum burstduty cycle. this duty cycle may be greater than the duty cycle of the psync input. once the duty cycle of the psync input is greater than the ds3988? minimum duty cycle, the output? duty cycle will track the psync? duty cycle. leaving psync low (0% duty cycle) disables the gan and gbn outputs in dpwm slave mode. note 5: this is the maximum lamp frequency duty cycle that will be generated at any of the gan or gbn outputs. note 6: i 2 c interface timing shown is for fast-mode (400khz) operation. this device is also backward compatible with i 2 c stan- dard-mode timing. note 7: after this period, the first clock pulse can be generated. note 8: c b ?otal capacitance allowed on one bus line in picofarads. note 9: eeprom write time applies to all the eeprom memory. eeprom write begins after a stop condition occurs. note 10: guaranteed by design. parameter symbol conditions min typ max units scl clock frequency f scl (note 6) 0 400 khz bus free time between stop andstart conditions t buf 1.3 ? hold time (repeated) startcondition t hd:sta (note 7) 0.6 ? low period of scl t low 1.3 ? high period of scl t high 0.6 ? data hold time t hd:dat 0 0.9 ? data setup time t su:dat 100 ns start setup time t su:sta 0.6 ? sda and scl rise time t r (note 8) 20 + 0.1c b 300 ns sda and scl fall time t f (note 8) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 ? sda and scl capacitive loading c b (note 8) 400 pf eeprom write time t w (note 9) 20 30 ms nonvolatile memory characteristics(v cc = +4.5v to +5.5v) parameter symbol conditions min typ max units eeprom write cycles +70? (note 10) 50,000 cycles downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller _____________________________________________________________________ 5 active supply current vs. supply voltage ds3988 toc01 supply voltage (v) supply current (ma) 5.3 4.7 5.1 4.9 7 9 11 13 15 17 19 5 4.5 5.5 f lf:osc = 71khz gate q c = 3.5nc dpwm = 100% dpwm = 50% dpwm = 10% svm = 0v active supply current vs. temperature ds3988 toc02 temperature ( c) supply current (ma) 60 35 10 -15 11 12 13 14 15 16 17 18 19 2010 -40 85 f lf:osc = 71khz gate q c = 3.5nc dpwm = 100% v cc = 4.5v v cc = 5.0v v cc = 5.5v internal frequency change vs. temperature ds3988 toc03 temperature ( c) frequency change (%) 60 35 -15 10 -3 -2 -1 0 1 2 3 4 -4 -40 85 lamp frequency dpwm frequency typical operation at 12v ds3988 toc04 10 s 5.0v g a 10 s 5.0v g b 10 s 2.0v lcm 10 s 2.0v ovd burst dimming at 150hz and 10% ds3988 toc08 1ms 5.0v g a 1ms 5.0v g b 1ms 2.0v lcm 1ms 2.0v ovd typical operation at 15v ds3988 toc05 10 s 5.0v g a 10 s 5.0v g b 10 s 2.0v lcm 10 s 2.0v ovd typical operation at 18v ds3988 toc06 10 s 5.0v g a 10 s 5.0v g b 10 s 2.0v lcm 10 s 2.0v ovd typical startup with svm ds3988 toc07 2ms 2.0v svm 2ms 5.0v g b 2ms 2.0v lcm 2ms 2.0v ovd t ypical operating characteristics (v cc = +5.0v, t a = +25?, unless otherwise noted.) downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller 6 _____________________________________________________________________ t ypical operating characteristics (continued) (v cc = +5.0v, t a = +25?, unless otherwise noted.) burst dimming at 150hz and 50% ds3988 toc09 1ms 5.0v g a 1ms 5.0v g b 1ms 2.0v lcm 1ms 2.0v ovd soft-start at v inv = 18v ds3988 toc10 50 s 5.0v g a 50 s 5.0v g b 50 s 2.0v lcm 50 s 2.0v ovd lamp strike?xpanded view ds3988 toc11 1ms 5.0v g a 1ms 5.0v g b 1ms 2.0v lcm 1ms 2.0v ovd lamp strike with open lamp autoretry enabled ds3988 toc12 50ms 5.0v g a 50ms 5.0v g b 50ms 2.0v lcm 50ms 2.0v ovd lamp strike with open lamp autoretry disabled ds3988 toc13 50ms 5.0v g a 50ms 5.0v g b 50ms 2.0v lcm 50ms 2.0v ovd staggered burst dimming start ds3988 toc14 0.1ms 5.0v ga 1 0.1ms 5.0v ga 2 0.1ms 5.0v ga 3 0.1ms 5.0v ga 4 lamp-out (lamp opened) autoretry disabled ds3988 toc15 0.5ms 5.0v g a 0.5ms 5.0v g b 0.5ms 2.0v lcm 0.5ms 2.0v ovd lamp-out (lamp opened) autoretry enabled ds3988 toc16 50ms 5.0v g a 50ms 5.0v g b 50ms 2.0v lcm 50ms 2.0v ovd downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller _____________________________________________________________________ 7 pin description pins by channel (n = 1?) name ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 ch 8 description gan 1 5 9 14 19 25 29 33 mosfet a gate drive. connect directly to logic-level mode n-channel mosfet. leave open if channel is unused. gbn 2 6 10 15 20 26 30 34 mosfet b gate drive. connect directly to logic-level mode n-channel mosfet. leave open if channel is unused. lcmn 371 1 16 21 27 31 35 lamp current monitor input. lamp current ismonitored by measuring a voltage across a resistor placed in series with the low-voltage side of the lamp. leave open if channel is unused. ovdn 481 2 17 22 28 32 36 overvoltage detection. lamp voltage ismonitored through a capacitor-divider placed on the high-voltage side of the transformer. leave open if channel is unused. name pin description gnd 13, 18, 24, 45 ground connection v cc 23, 48 power-supply connection sda 37 serial data input/output. i 2 c bidirectional data pin, which requires a pullup resistor to realize high logic levels. scl 38 serial clock input. i 2 c clock input. fault 39 fault output. active-low, open-drain, requires external pullup resistor to realize high logic levels. lsync 40 lamp frequency input/output. this pin is the input for an externally sourced lamp frequency when the ds3988 is configured as a lamp frequency receiver. if the ds3988 is configured as a lamp frequency source (i.e., the lamp frequency is generated internally), the frequency is output on this pin for use by other lamp frequency receiver ds3988s. losc 41 lamp oscillator resistor adjust. a resistor to ground on this lead sets the frequency of the lamp oscillator. a0 42 address select input. determines the ds3988? i 2 c slave address. psync 43 dpwm input/output. this pin is the input for an externally generated dpwm signal when the ds3988 is configured as a dpwm receiver. if the ds3988 is configured as a dpwm source (i.e., the dpwm signal is generated internally), the dpwm signal is output on this pin for use by other dpwm receiver ds3988s. posc 44 dpwm oscillator resistor adjust. a resistor to ground on this lead sets the frequency of the dpwm oscillator(dimming clock). this lead can optionally accept a 22.5hz to 440hz clock as the source timing for the internal dpwm signal. bright 46 analog brightness control input. used to control dpwm dimming. ground when using a pwm signal atpsync to control brightness. svm 47 supply voltage monitor input. used to monitor the inverter voltage for undervoltage conditions. downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller 8 _____________________________________________________________________ functional diagram i 2 c- compatible interface 8-byte user memory eeprom system enable/por eight independent ccfl controllers channel fault channel enable [40khz to 80khz] 8-phase generator x512 pll 01 10 01 mux rgso bit at cr1.4 ramp generator mux poscs bit at cr1.1 mux dpss bit at cr1.3 dpwm signal gnd gbn gan mosfet gate drivers ovdn overvoltage detection lcmnlamp current monitor fault handling 40khz to 80khz sda i 2 c device configuration port lamp frequency input/output external resistor lamp frequency set dpwm signal input/output analog brightness control external resistor dpwm frequency set/ dpwm clock input scl a0 fault lsync losc psync bright posc [20.48mhz to 40.96mhz] 22.5hz to 440hz 40khz to 80khz oscillator ( 5%) 22.5hz to 440hz oscillator ( 5%) lfss bit at cr1.2 dpss bit at cr1.3 uvlo v cc [4.5v to 5.5v] svm supply voltage monitor 2.0v control registers ds3988 downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller _____________________________________________________________________ 9 ds3988 overvoltage lamp overcurrent lse bit at cr1.0 lamp regulation channel enable channel fault digital ccfl controller lamp out 1 of 8 channels 400mv lcmlamp current monitor 1.0v 2.0v 1.0v 256 lamp cycle integrator peak detect/ hold peak detect g a ovdovervoltage detection mosfetgate drivers g b gate drivers 256 lamp cycle integrator dpwm signal 512 x lamp frequency [20.48mhz to 40.96mhz] phased lamp frequency [40khz to 80khz] figure 1. per channel logic diagram detailed description the ds3988 uses a push-pull drive scheme to converta dc voltage (5v to 24v) to the high-voltage (600v rms to 1200v rms ) ac waveform that is required to power the ccfls. the push-pull drive scheme uses a minimalnumber of external components, which reduces assembly cost and makes the printed circuit board (pc board) design easy to implement. the push-pull drive scheme also provides an efficient dc-to-ac conversion and produces near-sinusoidal waveforms. each ds3988 channel drives two logic-level n-channel mosfets that are connected between the ends of a step-up transformer and ground (see figure 1 and the typical operating circuit ). the transformer has a cen- ter tap on the primary side that is connected to a dcvoltage supply. the ds3988 alternately turns on the two mosfets to create the high-voltage ac waveform on the secondary side. by varying the duration of the mosfet turn-on times, the controller is able to accu- rately control the amount of current flowing through the ccfl. a resistor in series with the ccfl? ground connection enables current monitoring. the voltage across this resistor is fed to the lamp current monitor (lcm) input on the ds3988. the ds3988 compares the peak resistor voltage against an internal reference voltage to deter- mine the duty cycle for the mosfet gates. each ccfl receives independent current monitoring and control, which results in equal brightness across all of the lamps and maximizes the lamp? brightness and lifetime. eeprom registers and i 2 c-compatible serial interface the ds3988 uses an i 2 c-compatible serial interface for communication with the on-board eeprom configura- tion registers and user memory. the configuration regis- ters?our soft-start profile registers (ssp1/2/3/4) and two control registers (cr1/2)?llow the user to cus- tomize many ds3988 parameters such as the soft-start ramp rate, the lamp and dimming frequency sources, fault-monitoring options, and channel enabling/disabling. the eight bytes of nonvolatile user memory can be used to store manufacturing data such as date codes, serial numbers, or product identification numbers. the device is shipped from the factory with the configu- ration registers programmed to a set of default configu- ration parameters. to inquire about custom factory programming, email mixedsignal.apps@dalsemi.com. downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller 10 ____________________________________________________________________ channel phasing the lamp-frequency mosfet gate turn-on times areequally phased among the eight channels during the burst period. this reduces the inrush current that would result from all lamps switching simultaneously, and hence eases the design requirements for the dc sup- ply. figure 2 details how the eight channels are phased. note that it is the lamp-frequency signals that are phased, not the dpwm signals. lamp dimming control (dpwm) the ds3988 uses a digital pulse-width modulated(dpwm) signal (22.5hz to 440hz) to provide efficient and precise lamp dimming. during the high period of the dpwm cycle, the lamps are driven at the selected lamp frequency (40khz to 80khz) as shown in figure 6. this part of the cycle is called the ?urst?period because of the lamp frequency burst that occurs dur- ing this time. during the low period of the dpwm cycle, the controller disables the mosfet gate drivers so the lamps are not driven. this causes the current to stop flowing in the lamps, but the time is short enough to keep the lamps from de-ionizing. dimming is increased/ decreased by adjusting (i.e., modulating) the duty cycle of the dpwm signal. the ds3988 can generate its own dpwm signal internally (set dpss = 0 in cr1), which can then be sourced to other ds3988s if required, or the dpwm signal can be supplied from an external source (set dpss = 1 in cr1). 123456 78 2 3 4567 8 1 234 567 8 variable mosfet gate duty cycle 1 8 ga1 channel sequence gb1ga2 gb2 ga3 gb3ga4 gb4ga5 gb5 ga6 gb6 ga7gb7 ga8 gb8 mosfet gate- drive signals at lamp frequency dimming clock (dpwm) frequency figure 2. channel phasing detail downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller ____________________________________________________________________ 11 to generate the dpwm signal internally, the ds3988requires a clock (referred to as the dimming clock) to set the dpwm frequency. the user can supply the dim- ming clock by setting poscs = 1 in cr1 and applying an external 22.5hz to 440hz signal at the posc pin, or ds3988? clock can be generated by the ds3988? oscillator (set poscs = 0 in cr1), in which case the frequency is set by an external resistor at the posc pin. these two dimming clock options are shown in figure 3. regardless of whether the dimming clock is generated internally or sourced externally, the posc1 and posc2 bits in cr2 must be set to match the desired dimming clock frequency. when the dpwm signal is generated internally, its duty cycle (and, thus, the lamp brightness) is controlled by a user-applied analog voltage at the bright input. a bright voltage less than 0.5v will cause the ds3988 to operate with the minimum burst duty cycle, providing the lowest brightness setting, while any voltage greater than 2.0v will cause a 100% burst duty cycle (i.e., lamps always being driven), which provides the maximum brightness. for voltages between 0.5v and 2v the dutycycle will vary linearly between the minimum and 100%. the internally generated dpwm signal is available at the psync i/o pin (set rgso = 0 in cr1) for sourcing to other ds3988s, if any, in the circuit. this allows all ds3988s in the system to be synchronized to the same dpwm signal. the ds3988 that is generating the dpwm signal for other ds3988s in the system is referred to as the dpwm source. when the dpwm signal is provided by an external source, either from the psync pin of another ds3988 or from some other user-generated source, it is input into the psync i/o pin of the ds3988. in this mode, the bright and posc inputs are disabled and should be grounded (see figure 4). when multiple ds3988s are used in a design, ds3988s configured to use externally generated dpwm signals are referred to as dpwm receivers. lamp frequency configuration the ds3988 can generate its own lamp frequency clockinternally (set lfss = 0 in cr1), which can then be sourced to other ds3988s if required, or the lamp clock can be supplied from an external source (set lfss = 1 in cr1). when the lamp clock is internally generated, the frequency (40khz to 80khz) is set by an external resistor at the losc. in this case, the ds3988 can act as a lamp frequency source because the lamp clock is output at the lsync i/o pin for synchronizing any other ds3988s configured as lamp frequency receivers. the ds3988 acts as a lamp frequency receiver when the lamp clock is supplied externally. in this case, a 40khz to 80khz clock must be supplied at the lsync i/o. the external clock can originate from the lsync i/o of a ds3988 configured as a lamp frequency source or from some other source. brightpsync (output) posc 2.0v 0.5v 22.5hz to 440hz resistor to set the dimming frequency dpwm signal analog dimming control voltage resistor-set dimming clock brightpsync (output) posc 2.0v 0.5v 22.5hz to 440hz 22.5hz to 440hz dpwm signal external dimming clock analog dimming control voltage external dimming clock figure 3. dpwm source configuration options brightpsync (output) posc 22.5hz to 440hz dpwm signal figure 4. the dpwm receiver configuration downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller 12 ____________________________________________________________________ configuring systems with multiple ds3988s the source and receiver options for the lamp frequencyclock and dpwm signal allow multiple ds3988s to be synchronized in systems requiring more than 8 lamps. the lamp and dimming clocks can either be generated on board the ds3988 using external resistors to set thefrequency, or they can be sourced by the host system to synchronize the ds3988 to other system resources. figure 5 shows various multiple ds3988 configurations that allow both lamp and/or dpwm synchronization for all ds3988s in the system. 2.0v bright lamp frequency source dpwm source psynclsync posc losc 0.5v resistor-set dimming frequency resistor-set lamp frequency ds3988 bright lamp frequency receiver dpwm receiver psynclsync posc losc ds3988 2.0v bright lamp frequency source dpwm source psynclsync posc losc 0.5v analog brightness analog brightness resistor-set lamp frequency dimming clock (22.5hz to 440hz) dpwm signal (22.5hz to 440hz) ds3988 bright lamp frequency receiver dpwm receiver psynclsync posc losc ds3988 bright lamp frequency source dpwm receiver psynclsync posc losc resistor-set lamp frequency ds3988 bright lamp frequency receiver dpwm receiver psynclsync posc losc ds3988 2.0v bright lamp frequency receiver dpwm source psynclsync posc losc 0.5v resistor-set dimming frequency ds3988 bright lamp frequency receiver dpwm receiver psynclsync posc losc ds3988 2.0v bright lamp frequency receiver dpwm source psynclsync posc losc 0.5v analog brightness analog brightness lamp clock (40khz to 80khz) dimming clock (22.5hz to 440hz) lamp clock (40khz to 80khz) dpwm signal (22.5hz to 440hz) lamp clock (40khz to 80khz) ds3988 bright lamp frequency receiver dpwm receiver psynclsync posc losc ds3988 bright lamp frequency receiver dpwm receiver psynclsync posc losc ds3988 bright lamp frequency receiver dpwm receiver psynclsync posc losc ds3988 figure 5. frequency configuration options for designs using multiple ds3988s downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller ____________________________________________________________________ 13 dpwm soft-start at the beginning of each lamp burst, the ds3988 pro-vides a soft-start that slowly increases the mosfet gate-driver duty cycle (see figure 6). this minimizes the possibility of audible transformer noise that could result from current surges in the transformer primary. the soft-start length is fixed at 16 lamp cycles, but the soft-start ramp profile is programmable through the four soft-start profile registers (ssp1/2/3/4) and can be adjusted to match the application. there are seven dif-ferent driver duty cycles to select from to customize the soft-start ramp (see table 1). the available duty cycles range from 0% to 19% in ~3% increments. in addition, the mosfet duty cycle from the last lamp cycle of the previous burst can be used as part of the soft-start ramp by using the most recent value duty-cycle code. each programmed mosfet gate duty cycle repeats twice to make up the 16 soft-start lamp cycles. 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ssp1. 0-3 lamp current soft-start profile register soft-start soft-start (expanded) 22.5hz to 440hz dpwm signal lamp current lamp cycle gan/gbn mosfet gate drivers programmable soft-start profile with increasing mosfet pulse widths over a 16 lamp cycle period results in a linear ramp in lamp current. ssp1. 4-7 ssp2. 0-3 ssp2. 4-7 ssp3. 0-3 ssp3. 4-7 ssp4. 0-3 ssp4. 4-7 1 figure 6. digital pwm dimming and soft-start downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller 14 ____________________________________________________________________ setting the lamp and dimming clock (dpwm) frequencies using external resistors both the lamp and dimming clock frequencies can beset using external resistors. the resistance required for either frequency can be determined using the following formula: where k = 1600k ? ? khz for lamp frequency calcula- tions. when calculating the resistor value for the dim- ming clock frequency, k will be one of four values as determined by the desired frequency and the poscr0 and poscr1 bit settings as shown in the control register 2 (cr2) table 4 in the detailed register descriptions section. example: selecting the resistor values to configure a ds3988 to have a 50khz lamp frequency and a 160hzdimming clock frequency: for this configuration, poscr0 and poscr1 must be programmed to 1 and 0, respectively, to select 90hz to 220hz as the dimming clock frequency range. this sets k for the dimming clock resistor (r posc ) calculation to 4k ?? khz. for the lamp frequency resistor (r losc ) cal- culation, k = 1600k ?? khz, which allows the lamp fre- quency k value regardless of the frequency. theformula above can now be used to calculate the resis- tor values for r losc and r posc as follows: supply monitoring the ds3988 monitors both the transformer? dc supplyand its own v cc supply to ensure that both voltage lev- els are adequate for proper operation.the inverter? transformer supply (v inv ) is monitored using an external resistor-divider that is the input into a comparator (see figure 7) with a 2v threshold. using the equation below to determine the resistor values, the supply voltage monitor (svm) trip point (v trip ) can be customized to shut off the inverter when the trans- former? input voltage drops below any specified value. operating with the transformer? supply at too low of a level can prevent the inverter from reaching the strike voltage and could potentially cause numerous other problems. proper use of the svm can prevent theseproblems. if desired, the svm can be disabled by con- necting the svm pin to v cc . the v cc monitor is used as a 5v supply undervoltage lockout (uvlo) that prevents operation when the ds3988does not have adequate voltage for its analog circuitry to operate or to drive the external mosfets. the v cc moni- tor features hysteresis to prevent v cc noise from causing spurious operation when v cc is near the trip point. this monitor cannot be disabled by any means. fault monitoring the ds3988 provides extensive fault monitoring foreach channel. it can detect open-lamp, lamp overcur- rent, failure to strike, and overvoltage conditions. the ds3988 can be configured to disable all channels if one or more channels enter a fault state, or it can be configured to disable only the channel where the fault occurred. once a fault state has been entered, the fault output is asserted and the channel(s) remain disabled until either the ds3988 is power-cycled or theinverter? dc supply is power-cycled. the ds3988 can also be configured to automatically attempt to clear a detected fault (except lamp overcurrent) by restriking the lamp, as explained in step 4. configuration bits for thefault monitoring options are located in cr1 and cr2. v rr r trip . = + ?? ? ?? ? 20 12 1 r k khz khz k r k khz khz k loscposc , . . = ? = = ? = 1600 50 32 4 0 160 25 0 ? ? ? ? r k f osc osc = v inv 2.0v svm example: r 1 = 10k ? , r 2 = 40k ? sets an svm trip point of 10v r 2 r 1 ds3988 figure 7. setting the svm threshold voltage downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller ____________________________________________________________________ 15 figure 8 shows a flowchart of how the ds3988 controls and monitors each lamp. the steps are as follows: 1) supply check?he lamps will not turn on unless the ds3988 supply voltage is 4.5v and the voltage at the supply voltage monitor (svm) input is 2v. 2) strike lamp?hen both the ds3988 and the dcinverter supplies are above the minimum values, the ds3988 will attempt to strike each enabled lamp for 768 lamp cycles [1 lamp cycle (seconds) = 1/lamp frequency (hertz)]. if the lamp doesn? strike during that time, the ds3988 will go into a fault-handling stage (step 4). the ds3988 detects that the lamp has struck by measuring the current flow through the lamp. also, if an overvoltage event is detected during the strike attempt, the ds3988 will disable the mosfet gate drivers and go to the fault-han- dling stage. if a lamp overcurrent is detected, the ds3988 will immediately enter a fault state. 3) run lamponce the lamp is struck, the ds3988 adjusts the mosfet gate duty cycle to optimize the lamp current. the lamp current sampling rate is user-selectable with the lsr0 and lsr1 bits in cr2. if the lamp current ever drops below the open lamp refer- ence point for 256 lamp cycles, the lamp is consid- ered extinguished. if this occurs or if an overvoltage event is detected while the lamp is running, the ds3988 will disable the mosfet gate drivers and go to the fault-handling stage. if a lamp overcurrent is detected, the ds3988 will immediately enter a fault state. 4) fault handling?he ds3988 can be configured to automatically restrike the lamp(s) in an attempt toclear the detected fault condition (except for lamp overcurrent faults). the automatic retry will make up to 15 re-strike attempts before entering a fault state. between each of the 15 retries, the controller will wait 1024 lamp cycles. if after any of the retries the fault has cleared, normal operation will resume. in the case of a lamp overcurrent fault, the ds3988 will skip the automatic retry even if it is enabled and will immediately enter a fault state. device and inverter supplies above minimum level? reset fault counter and fault output fault wait [1024 lamp cycles] fault-handling stage 4 fault fault fault lamp strikes correctly lamp overcurrent [instantaneous response if enabled with the loc bit at cr1.0] strike lamp lamp strike timeout [lamp out for 768 lamp cycles] lamp extinguished [lamp out for 256 lamp cycles] overvoltage [256 lamp cycles] run lamp fault fault fault mosfet gate drivers enabled autoretry enabled? [ard bit at cr1.5] increment fault counter fault state [activate fault output] fault counter = 15? 2 3 1 yes no no yes yes figure 8. fault-handling flow chart downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller 16 ____________________________________________________________________ detailed register descriptions the ds3988? register map is shown in table 1.detailed register and bit descriptions follow in the sub- sequent tables. soft-start profile (sspx) registers ?ach of the four soft-start profile registers (ssp1?) contains two 4-bitcodes that determine the mosfet? duty cycle (mdc) for two clock cycles each (see figure 6) at the begin- ning of each dpwm burst. table 2 shows the duty cycles that correspond to each code. selecting the most recent value instructs the ds3988 to use the mosfet duty cycle that was used for the last lamp cycle of the previous burst. byte address byte name factory default* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f0h ssp1 21h mdc code for soft-start lamp cycles 3, 4 mdc code for soft-start lamp cycles 1, 2 f1h ssp2 43h mdc code for soft-start lamp cycles 7, 8 mdc code for soft-start lamp cycles 5, 6 f2h ssp3 65h mdc code for soft-start lamp cycles 11, 12 mdc code for soft-start lamp cycles 9, 10 f3h ssp4 77h mdc code for soft-start lamp cycles 15, 16 mdc code for soft-start lamp cycles 13, 14 f4h cr1 00h dpd frs ard rgso dpss lfss poscs loc f5h cr2 08h ld2 ld1 ld0 lsr1 lsr0 poscr1 poscr0 umwp f6h cr3 00h do not modify. if it has been modified, restore to all zeros. f7h reserved f8-ffh user memory 00h ee ee ee ee ee ee ee ee * all the configuration settings are saved in nonvolatile (eeprom) memory. table 1. register map table 2. mosfet duty cycle (mdc) codes for soft-start settings mdc code (binary)* mosfet duty cycle x000 fixed at 0% x001 fixed at 3% x010 fixed at 6% x011 fixed at 9% x100 fixed at 13% x101 fixed at 16% x110 fixed at 19% x111 most recent value * the most significant bit of each mdc code is ignored. downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller ____________________________________________________________________ 17 table 3. control register 1 (cr1) bit name function 0 loc lamp overcurrent. 0 = lamp overcurrent detection disabled. 1 = lamp overcurrent detection enabled. note: gate duty cycle changes during soft-start larger than 5% can cause false loc fault. 1 poscs posc select. see poscr0 and poscr1 bits in control register 2 to select the oscillator range.0 = connect posc to ground with a resistor to set the dimming frequency. 1 = connect posc to an external 22.5hz to 440hz dimming clock to set the dimming frequency. 2 lfss lamp frequency source select. 0 = lamp frequency source mode. the lamp frequency is generated internally and sourced at the lsync output for use by lamp frequency receivers. 1 = lamp frequency receiver mode. the lamp frequency must be provided at the lsync input. 3 dpss dpwm signal source select. 0 = d p w m sour ce m od e. d p w m si g nal i s g ener ated i nter nal l y, and can b e outp ut at p s y n c p i n ( see rgs o b i t) . 1 = dpwm receiver mode. dpwm signal is generated externally and supplied at the psync input. 4 rgso ramp generator source option. 0 = sources dpwm at the psync output. 1 = sources the internal ramp generator at psync output. 5 ard autoretry disable. 0 = autoretry function enabled. 1 = autoretry function disabled. 6 frs fault response select.0 = disable only the malfunctioning channel. 1 = disable all channels upon fault detection at any channel. 7 dpd dpwm disable. 0 = dpwm function enabled. 1 = dpwm function disabled. dpwm set to 100% duty cycle. downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller 18 ____________________________________________________________________ table 4. control register 2 (cr2) bit name function 0 umwp user memory write protect.0 = user memory write access blocked 1 = user memory write access permitted 1 poscr0 dpwm oscillator range select. when using an external source for the dimming clock, these bits mustbe set to match the external oscillator? frequency. when using a resistor to set the dimming frequency, these bits plus the external resistor control the frequency. poscr1 poscr0 dimming clock (dpwm) frequency range (hz) k (k ? ? khz) 00 22.5 to 55.0 1 01 45 to 110 2 10 90 to 220 4 2 poscr1 11 180 to 440 8 lamp sample rate select. determines the feedback sample rate of the lcm inputs lsr1 lsr0 selected lamp sample rate example sample rate if lamp frequency is 50khz 3 lsr0 00 4 lamp frequency cycles 12500hz 01 8 lamp frequency cycles 6250hz 10 16 lamp frequency cycles 3125hz 4 lsr1 11 32 lamp frequency cycles 1563hz lamp disable. used to disable channels if all 8 are not required for an application. ld2 ld1 ld0 channels disabled number of active lamp channels 00 0 all channels enabled 8 5 ld0 00 18 7 01 0 4/8 6 01 1 2/4/8 5 6 ld1 10 0 2/4/6/8 4 10 12 / 4 /6/7/8 3 11 02 / 3 /4/6/7/8 2 7 ld2 11 12 / 3 /4/5/6/7/8 1 downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller ____________________________________________________________________ 19 i 2 c definitions the following terminology is commonly used todescribe i 2 c data transfers. master device: the master device controls the slave devices on the bus. the master device generates sclclock pulses, start, and stop conditions. slave devices: slave devices send and receive data at the master? request.bus idle or not busy: time between stop and start conditions when both sda and scl are inactive and intheir logic-high states. start condition: a start condition is generated by the master to initiate a new data transfer with a slave.transitioning sda from high to low while scl remains high generates a start condition. see the timing dia- gram for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioningsda from low to high while scl remains high gener- ates a stop condition. see the timing diagram for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data transferto indicate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identically to a nor- mal start condition. see the timing diagram for applica-ble timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid andunchanged during the entire high pulse of scl plus the setup and hold time requirements (see figure 9). data is shifted into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time (see figure 9) before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master gener- ates all scl clock pulses including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowl- edgement (ack) or not acknowledge (nack) is alwaysthe 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a zero during the 9th bit. a device per- forms a nack by transmitting a one during the 9th bit. timing (figure 9) for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. figure 9. i 2 c timing diagram sdascl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop note: timing is reference to v il(max) and v ih(min) . start downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller 20 ____________________________________________________________________ byte write: a byte write consists of 8 bits of informa- tion transferred from the master to the slave (most sig-nificant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the mas- ter are done according to the bit-write definition and the acknowledgement is read using the bit-read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nackfrom the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to terminate communication so the slave will return control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave addressing byte sent immediatelyfollowing a start condition. the slave address byte (figure 10) contains the slave address in the most signifi- cant seven bits and the r/ w bit in the least significant bit. the ds3988? slave address is 101000a 0 (binary), where a 0 is the value of the address pin (a 0 ). the address pin allows the device to respond to one of twopossible slave addresses. by writing the correct slave address with r/ w = 0, the master writes data to the slave. if r/ w = 1, the master reads data from the slave. if an incorrect slave address is written, the ds3988 willassume the master is communicating with another i 2 c device and ignore the communications until the nextstart condition is sent. memory address: during an i 2 c write operation, the master must transmit a memory address to identify thememory location where the slave is to store the data. the memory address is always the second byte trans- mitted during a write operation following the slave address byte. i 2 c communication writing a data byte to a slave: the master must gen- erate a start condition, write the slave address byte(r/ w = 0), write the memory address, write the byte of data, and generate a stop condition. remember themaster must read the slave? acknowledgement during all byte write operations. see figure 11 for more detail. acknowledge polling: any time eeprom is written, the ds3988 requires the eeprom write time (t w ) after the stop condition to write the contents to eeprom.during the eeprom write time, the ds3988 will not acknowledge its slave address because it is busy. it is possible to take advantage of that phenomenon by repeatedly addressing the ds3988, which allows the next byte of data to be written as soon as the ds3988 is ready to receive the data. the alternative to acknowl- edge polling is to wait for a maximum period of t w to elapse before attempting to write again to the ds3988.eeprom write cycles: the number of times the ds3988? eeprom can be written before it fails isspecified in the nonvolatile memory characteristics table. this specification is shown at the worst-casewrite temperature. the ds3988 is typically capable of handling many additional write cycles when the writes are performed at room temperature. reading a data byte from a slave: to read a single byte from the slave the master generates a start condi-tion, writes the slave address byte with r/ w = 0, writes the memory address, generates a repeated start condi-tion, writes the slave address with r/ w = 1, reads the data byte with a nack to indicate the end of the trans- fer, and generates a stop condition. see figure 11 for more detail. figure 10. ds3988s slave address byte 7-bit slave address most significant bit a 0 pin value determines read or write r/w 1 01 0 00 a 0 downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller ____________________________________________________________________ 21 applications information addressing multiple ds3988s on a common i 2 c bus each ds3988 responds to one of two possible slaveaddresses based on the state of the address input (a 0 ). for information about device addressing see the i 2 c communications section. power-supply decoupling to achieve best results, it is recommended that eachv cc pin is decoupled with a 0.01? or a 0.1? capacitor to gnd. use high-quality, ceramic, surface-mount capac- itors, and mount the capacitors as close as possible to the v cc and gnd pins to minimize trace inductance. setting the rms lamp current resistor r8 in the typical operating circuit (figure 12)sets the lamp current. r8 = 140 ? corresponds to a 5ma rms lamp current as long as the current waveform is approximately sinusoidal. the formula to determinethe resistor value for a given sinusoidal lamp current is: component selection external component selection has a large impact on theoverall system performance and cost. the two most important external components are the transformers and n-channel mosfets. the transformer should be able to operate in the 40khz to 80khz frequency range of the ds3988, and the turns ratio should be selected so the mosfet drivers run at 28% to 35% duty cycle during steady state operation. the transformer must be able to withstand the high open-circuit voltage that will be used to strike the lamp. additionally, its primary/secondary resistance and inductance characteristics must be considered because they contribute significantly to determining the efficiency and transient response of the system. table 5 shows a transformer specification that has been utilized for a 12v inverter supply, 438mm x 2.2mm lamp design. the n-channel mosfet must have a threshold voltage that is low enough to work with logic-level signals, a low on-resistance to maximize efficiency and limit the n- channel mosfet? power dissipation, and a break- down voltage high enough to handle the transient. the breakdown voltage should be a minimum of 3x the inverter voltage supply. additionally, the total gate charge must be less than q g , which is specified in the recommended dc operating conditions table. these specifications are easily met by many of the dual n-channel mosfets now available in so-8 packages. table 6 lists suggested values for the external resistors and capacitors used in the typical operating circuit. r i lamp rms 8 1 2 () = figure 11. i 2 c communications examples xxxxxxxx 101 0 a 0 0 00 communications key write a single byte 8-bits address or data white boxes indicate the master is controlling sda notes 2) the first byte sent after a start condition is always the slave address followed by the read/write bit. shaded boxes indicate the slave is controlling sda start ack notack s sa a a p d ata memory address 101 0 a 0 0 00 101 0 a 0 0 00 read a single byte sa asr an p d ata memory address a pn sr stop repeated start 1) all bytes are sent most significant bit first. downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller 22 ____________________________________________________________________ table 5. transformer specifications parameter conditions min typ max units turns ratio (secondary/primary) (notes 11, 12, 13) 40 frequency 40 80 khz output power 6w output current 58m a primary dcr center tap to one end 200 m ? secondary dcr 500 ? primary leakage 12 ? secondary leakage 185 mh primary inductance 70 ? secondary inductance 500 mh center tap voltage 10.8 12 13.2 v 100ms minimum 2000 secondary output voltage continuous 1000 v rms table 6. resistor and capacitor selection guide designator qty value 25? tolerance (%) temperature coefficient notes r1 1 10k ? 1 r2 1 12.5k ? to 105k ? 1 see the setting the svm threshold voltage section. r3 1 20k ? to 40k ? 1 153ppm/? 2% or less total tolerance. see the lamp frequency configuration section to determine value. r4 1 18k ? to 45k ? 1 153ppm/? 2% or less total tolerance. see the lamp frequency configuration section to determine value. r5 1 4.7k ? 5 any grade r6 1 4.7k ? 5 any grade r7 1 4.7k ? 5 any grade r8 1/ch 140 ? 1 see the setting the rms lamp current section. c1 1/ch 100nf 10 x7r c ap aci tor val ue w i l l al so affe ct lc m bi as vol tag e d ur i ng p ow er - up . a l ar g er cap aci tor m ay cause a l ong er ti m e for v dcb to r e ach i ts nor m al op er ati ng p oi nt. c2 1/ch 10pf 5 ?000ppm/c 2kv to 4kv breakdown voltage required. c3 1/ch 27nf 5 x7r c ap aci tor val ue w i l l al so affe ct lc m bi as vol tag e d ur i ng p ow er - up . a l ar g er cap aci tor m ay cause a l ong er ti m e for v dcb to r e ach i ts nor m al op er ati ng p oi nt. c4 1/ch 33? 20 any grade c5 2/ds3988 0.1? 10 x7r place close to v cc and gnd on ds3988. note 11: primary should be bifilar wound with center tap connection. note 12: turns ratio is defined as secondary winding divided by the sum of both primary windings. note 13: 40:1 is the nominal turns ratio for driving a 438mm x 2.2mm lamp with a 12v supply. refer to an3375 for more information. downloaded from: http:///
ds3988 8-channel cold-cathode fluorescent lamp controller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 23 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. is a registered trademark of dallas semiconductor corporation. t ypical operating circuit package information for the latest package outline information, go towww.maxim-ic.com/dallaspackinfo . chip information transistor count: 70,200substrate connected to: ground ds3988 bright v cc v cc svm gangbn ovdn lcmn c1 lamp voltage monitor c3 r8 ccfl lamp transformer dual power mosfet supply voltage (5v 10% to 24v 10%) supply voltage (5v 10%) c2 r1 r2 c5 c4 lamp current monitor gnd psync lsync losc posc r3 r4 r5 r6 r7 configuration port f ault sda see notes 14, 15. scla0 analog brightness external digital pwm input/ internal digital pwm output external lamp frequency input/ internal lamp frequency output note 14: only one channel shown to simplify drawing. note 15: see the component selection section for recommended external components. figure 12. typical operating circuit downloaded from: http:///

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